<h2>Editing File: /opt/rh/gcc-toolset-11/root/usr/libexec/valgrind/power-altivec.xml</h2><form method='post'><textarea name='content' class='file-edit'>&lt;?xml version=&quot;1.0&quot;?&gt;
&lt;!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.

     Copying and distribution of this file, with or without modification,
     are permitted in any medium without royalty provided the copyright
     notice and this notice are preserved.  --&gt;

&lt;!DOCTYPE feature SYSTEM &quot;gdb-target.dtd&quot;&gt;
&lt;feature name=&quot;org.gnu.gdb.power.altivec&quot;&gt;
  &lt;vector id=&quot;v4f&quot; type=&quot;ieee_single&quot; count=&quot;4&quot;/&gt;
  &lt;vector id=&quot;v4i32&quot; type=&quot;int32&quot; count=&quot;4&quot;/&gt;
  &lt;vector id=&quot;v8i16&quot; type=&quot;int16&quot; count=&quot;8&quot;/&gt;
  &lt;vector id=&quot;v16i8&quot; type=&quot;int8&quot; count=&quot;16&quot;/&gt;
  &lt;union id=&quot;vec128&quot;&gt;
    &lt;field name=&quot;uint128&quot; type=&quot;uint128&quot;/&gt;
    &lt;field name=&quot;v4_float&quot; type=&quot;v4f&quot;/&gt;
    &lt;field name=&quot;v4_int32&quot; type=&quot;v4i32&quot;/&gt;
    &lt;field name=&quot;v8_int16&quot; type=&quot;v8i16&quot;/&gt;
    &lt;field name=&quot;v16_int8&quot; type=&quot;v16i8&quot;/&gt;
  &lt;/union&gt;

  &lt;reg name=&quot;vr0&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot; regnum=&quot;73&quot;/&gt;
  &lt;reg name=&quot;vr1&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr2&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr3&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr4&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr5&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr6&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr7&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr8&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr9&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr10&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr11&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr12&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr13&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr14&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr15&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr16&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr17&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr18&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr19&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr20&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr21&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr22&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr23&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr24&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr25&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr26&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr27&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr28&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr29&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr30&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;
  &lt;reg name=&quot;vr31&quot; bitsize=&quot;128&quot; type=&quot;vec128&quot;/&gt;

  &lt;reg name=&quot;vscr&quot; bitsize=&quot;32&quot; group=&quot;vector&quot;/&gt;
  &lt;reg name=&quot;vrsave&quot; bitsize=&quot;32&quot; group=&quot;vector&quot;/&gt;
&lt;/feature&gt;
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